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INTEGRATED CIRCUITS
NOTICE PLEASE SEE THE P87C552 DATA SHEET FOR NEW DESIGN-INS
87C552 80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
Product specification Supersedes data of 1998 Jan 19 IC20 Data Handbook 1998 May 01
Philips Semiconductors
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
87C552
DESCRIPTION
The 87C552 Single-Chip 8-Bit Microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The 87C552 has the same instruction set as the 80C51. Three versions of the derivative exist:
* 83C552--8k bytes mask programmable ROM * 80C552--ROMless version of the 83C552 * 87C552--8k bytes EPROM
The 87C552 contains a 8k x 8 a volatile 256 x 8 read/write data memory, five 8-bit I/O ports, one 8-bit input port, two 16-bit timer/event counters (identical to the timers of the 80C51), an additional 16-bit timer coupled to capture and compare latches, a 15-source, two-priority-level, nested interrupt structure, an 8-input ADC, a dual DAC pulse width modulated interface, two serial interfaces (UART and I2C-bus), a "watchdog" timer and on-chip oscillator and timing circuits. For systems that require extra capability, the 87C552 can be expanded using standard TTL compatible memories and logic. In addition, the 87C552 has two software selectable modes of power reduction--idle mode and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial ports, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities. The instruction set consists of over 100 instructions: 49 one-byte, 45 two-byte, and 17 three-byte. With a 16MHz crystal, 58% of the instructions are executed in 0.75s and 40% in 1.5s. Multiply and divide instructions require 3s.
FEATURES
* 80C51 central processing unit * 8k x 8 EPROM expandable externally to 64k bytes * An additional 16-bit timer/counter coupled to four capture registers
and three compare registers
* Two standard 16-bit timer/counters * 256 x 8 RAM, expandable externally to 64k bytes * Capable of producing eight synchronized, timed outputs * A 10-bit ADC with eight multiplexed analog inputs * Two 8-bit resolution, pulse width modulation outputs * Five 8-bit I/O ports plus one 8-bit input port shared with analog
inputs
* I2C-bus serial I/O port with byte oriented master and slave
functions
* Full-duplex UART compatible with the standard 80C51 * On-chip watchdog timer * 16MHz speed * Extended temperature ranges * OTP package available
ORDERING INFORMATION
EPROM S87C552-4A68 S87C552-4BA S87C552-5A68 TEMPERATURE C AND PACKAGE 0 to +70, Plastic Leaded Chip Carrier 0 to +70, Plastic Quad Flat Pack -40 to +85, Plastic Leaded Chip Carrier FREQ MHz 16 16 16 DRAWING NUMBER SOT188-3 SOT318-2 SOT188-3
NOTE: 1. For ROM and ROMless see data sheet 80C552/83C552
1998 May 01
2
853-1690 19336
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
87C552
BLOCK DIAGRAM
T0 3 T1 3 INT0 3 INT1 3 VDD VSS PWM0 PWM1 AVSS AVREF ADC0-7 SDA SCL 1 1
-+
AVDD
STADC
5
XTAL1 XTAL2 EA ALE PSEN 3 3 RD 0 AD0-7 2 A8-15 PARALLEL I/O PORTS AND EXTERNAL BUS SERIAL UART PORT 8-BIT PORT FOUR 16-BIT CAPTURE LATCHES 16 WR T0, T1 TWO 16-BIT TIMER/EVENT COUNTERS PROGRAM MEMORY 8k x 8 EPROM DATA MEMORY 256 x 8 RAM DUAL PWM ADC SERIAL I2C PORT
CPU
80C51 CORE EXCLUDING ROM/RAM
8-BIT INTERNAL BUS
T2 16-BIT TIMER/ EVENT COUNTERS
16
T2 16-BIT COMPARATORS WITH REGISTERS
COMPARATOR OUTPUT SELECTION
T3 WATCHDOG TIMER
3 P0 P1 P2 P3 TxD
3 RxD P5 P4 CT0I-CT3I
1
1 T2 RT2
1
4 CMSR0-CMSR5 CMT0, CMT1 RST EW
0 1 2
ALTERNATE FUNCTION OF PORT 0 ALTERNATE FUNCTION OF PORT 1 ALTERNATE FUNCTION OF PORT 2
3 4 5
ALTERNATE FUNCTION OF PORT 3 ALTERNATE FUNCTION OF PORT 4 ALTERNATE FUNCTION OF PORT 5
SU00211
1998 May 01
3
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
87C552
LOGIC SYMBOL
VSS VDD XTAL1 XTAL2 EA/VPP ALE/PROG PSEN AVSS AVDD AVref+ AVref- STADC PWM0 PWM1
PIN CONFIGURATIONS
9 10 PORT 0 LOW ORDER ADDRESS AND DATA BUS 26 CT0I CT1I CT2I CT3I T2 RT2 SCL SDA 27 43 PLASTIC LEADED CHIP CARRIER 1 61 60
44
PORT 1
ADC0-7 PORT 5
HIGH ORDER ADDRESS AND DATA BUS
CMSR0-5 PORT 4 RxD/DATA TxD/CLOCK INT0 INT1 T0 T1 WR RD
CMT0 CMT1 RST EW
SU00210
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Function P5.0/ADC0 VDD STADC PWM0 PWM1 EW P4.0/CMSR0 P4.1/CMSR1 P4.2/CMSR2 P4.3/CMSR3 P4.4/CMSR4 P4.5/CMSR5 P4.6/CMT0 P4.7/CMT1 RST P1.0/CT0I P1.1/CT1I P1.2/CT2I P1.3/CT3I P1.4/T2 P1.5/RT2 P1.6/SCL P1.7/SDA
Pin 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
Function P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD NC NC XTAL2 XTAL1 VSS VSS NC P2.0/A08 P2.1/A09 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15
Pin 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
Function PSEN ALE/PROG EA/VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 AVref- AVref+ AVSS AVDD P5.7/ADC7 P5.6/ADC6 P5.5/ADC5 P5.4/ADC4 P5.3/ADC3 P5.2/ADC2 P5.1/ADC1
PORT 3
PORT 2
SU00208
PLASTIC QUAD FLAT PACK PIN FUNCTIONS
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Function P4.1/CMSR1 P4.2/CMSR2 NC P4.3/CMSR3 P4.4/CMSR4 P4.5/CMSR5 Pin 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Function NC NC P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD NC NC NC XTAL2 XTAL1 IC VSS VSS VSS NC P2.0/A08 P2.1/A09 P2.2/A10 Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Function P2.3/A11 P2.4/A12 NC NC P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE/PROG EA/VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 Pin 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Function AVSS NC AVDD P5.7/ADC7 P5.6/ADC6 P5.5/ADC5 P5.4/ADC4 P5.3/ADC3 P5.2/ADC2 P5.1/ADC1 P5.0/ADC0 VDD IC STADC PWM0 PWM1 EW NC NC P4.0/CMSR0
80
65
1
64
P4.6/CMT0
P4.7/CMT1 RST P1.0/CT0I P1.1/CT1I P1.2/CT2I
PQFP
24
41
P1.3/CT3I
P1.4/T2 P1.5/RT2 P1.6/SCL P1.7/SDA P3.0/RxD P3.1/TxD P3.2/INT0
25
40
P0.1/AD1
P0.0/AD0 AVref- AVref+
NC = Not Connected IC = Internally Connected (do not use)
SU00209
1998 May 01
4
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
87C552
PIN DESCRIPTION
PIN NO. MNEMONIC VDD STADC PWM0 PWM1 EW P0.0-P0.7 PLCC 2 3 4 5 6 57-50 QFP 72 74 75 76 77 58-51 TYPE I I O O I I/O NAME AND FUNCTION Digital Power Supply: +5V power supply pin during normal operation, idle and power-down mode. Start ADC Operation: Input starting analog to digital conversion (ADC operation can also be started by software). Pulse Width Modulation: Output 0. Pulse Width Modulation: Output 1. Enable Watchdog Timer: Enable for T3 watchdog timer and disable power-down mode. Port 0: Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pull-ups when emitting 1s. Port 0 is also used to input the code byte during programming and to output the code byte during verification. Port 1: 8-bit I/O port. Alternate functions include: (P1.0-P1.5): Quasi-bidirectional port pins. (P1.6, P1.7): Open drain port pins. CT0I-CT3I (P1.0-P1.3): Capture timer input signals for timer T2. T2 (P1.4): T2 event input. RT2 (P1.5): T2 timer reset signal. Rising edge triggered. SCL (P1.6): Serial port clock line I2C-bus. SDA (P1.7): Serial port data line I2C-bus. Port 1 is also used to input the lower order address byte during EPROM programming and verification. A0 is on P1.0, etc. Port 2: 8-bit quasi-bidirectional I/O port. Alternate function: High-order address byte for external memory (A08-A15). Port 2 is also used to input the upper order address during EPROM programming and verification. A8 is on P2.0, A9 on P2.1, through A12 on P2.4. Port 3: 8-bit quasi-bidirectional I/O port. Alternate functions include: RxD(P3.0): Serial input port. TxD (P3.1): Serial output port. INT0 (P3.2): External interrupt. INT1 (P3.3): External interrupt. T0 (P3.4): Timer 0 external input. T1 (P3.5): Timer 1 external input. WR (P3.6): External data memory write strobe. RD (P3.7): External data memory read strobe. I/O O O I I/O I Port 4: 8-bit quasi-bidirectional I/O port. Alternate functions include: CMSR0-CMSR5 (P4.0-P4.5): Timer T2 compare and set/reset outputs on a match with timer T2. CMT0, CMT1 (P4.6, P4.7): Timer T2 compare and toggle outputs on a match with timer T2. Port 5: 8-bit input port. ADC0-ADC7 (P5.0-P5.7): Alternate function: Eight input channels to ADC. Reset: Input to reset the 87C552. It also provides a reset pulse as output when timer T3 overflows. Crystal Input 1: Input to the inverting amplifier that forms the oscillator, and input to the internal clock generator. Receives the external clock signal when an external oscillator is used. Crystal Input 2: Output of the inverting amplifier that forms the oscillator. Left open-circuit when an external clock is used. Digital ground. Program Store Enable: Active-low read strobe to external program memory.
P1.0-P1.7
16-23 16-21 22-23 16-19 20 21 22 23
10-17 10-15 16-17 10-13 14 15 16 17
I/O I/O I/O I I I I/O I/O
P2.0-P2.7
39-46
38-42, 45-47
I/O
P3.0-P3.7
24-31 24 25 26 27 28 29 30 31
18-20, 23-27 18 19 20 23 24 25 26 27 80, 1-2 4-8 80, 1-2 4-6 7, 8 71-64, 9 32
I/O
P4.0-P4.7
7-14 7-12 13, 14
P5.0-P5.7 RST XTAL1
68-62, 1 15 35
XTAL2 VSS PSEN
34 36, 37 47
31 34-36 48
O I O
1998 May 01
5
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
87C552
PIN DESCRIPTION (Continued)
PIN NO. MNEMONIC ALE/PROG PLCC 48 QFP 49 TYPE O NAME AND FUNCTION Address Latch Enable: Latches the low byte of the address during accesses to external memory. It is activated every six oscillator periods. During an external data memory access, one ALE pulse is skipped. ALE can drive up to eight LS TTL inputs and handles CMOS inputs without an external pull-up. This pin is also the program pulse input (PROG) during EPROM programming. External Access: When EA is held at TTL level high, the CPU executes out of the internal program ROM provided the program counter is less than 8192. When EA is held at TTL low level, the CPU executes out of external program memory. EA is not allowed to float. This pin also receives the 12.75V programming supply voltage (VPP) during EPROM programming. Analog to Digital Conversion Reference Resistor: Low-end. Analog to Digital Conversion Reference Resistor: High-end. Analog Ground Analog Power Supply
EA/VPP
49
50
I
AVREF- AVREF+ AVSS AVDD
58 59 60 61
59 60 61 63
I I I I
NOTE: 1. To avoid "latch-up" effect at power-on, the voltage on any pin at any time must not be higher or lower than VDD + 0.5V or VSS - 0.5V, respectively.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator, as shown in the logic symbol. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed.
IDLE MODE
In the idle mode, the CPU puts itself to sleep while some of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset.
RESET
A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. To insure a good power-on reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. At power-on, the voltage on VDD and RST must come up at the same time for a proper start-up.
POWER-DOWN MODE
In the power-down mode, the oscillator is stopped and the instruction to invoke power-down is the last instruction executed. Only the contents of the on-chip RAM are preserved. A hardware reset is the only way to terminate the power-down mode. The control bits for the reduced power modes are in the special function register PCON. Table 1 shows the state of the I/O ports during low current operating modes.
Table 1. External Pin Status During Idle and Power-Down Modes
MODE Idle Idle Power-down Power-down PROGRAM MEMORY Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT 0 Data Float Data Float PORT 1 Data Data Data Data PORT 2 Data Address Data Data PORT 3 Data Data Data Data PORT 4 Data Data Data Data PWM0/ PWM1 High High High High
1998 May 01
6
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
87C552
Serial Control Register (S1CON) - See Table 2
S1CON (D8H)
CR2 ENS1 STA STO SI AA CR1 CR0
Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation.
Table 2. Serial Clock Rates
BIT FREQUENCY (kHz) AT fOSC CR2 0 0 0 0 1 1 1 1 CR1 0 0 1 1 0 0 1 1 CR0 0 1 0 1 0 1 0 1 6MHz 23 27 31.25 37 6.25 50 100 0.25 < 62.5 0 to 225 12MHz 47 54 62.5 75 12.5 100 200 0.5 < 62.5 0 to 224 16MHz 62.5 71 83.3 100 17 133 1 267 1 0.67 < 56 0 to 223 fOSC DIVIDED BY 256 224 192 160 960 120 60 96 x (256 - (reload value Timer 1)) Timer 1 in Mode 2.
NOTE: 1. These frequencies exceed the upper limit of 100kHz of the I2C-bus specification and cannot be used in an I2C-bus application.
ABSOLUTE MAXIMUM RATINGS1, 2, 3
PARAMETER Storage temperature range Voltage on EA/VPP to VSS Voltage on any other pin to VSS Input, output DC current on any single I/O pin Power dissipation (based on package heat transfer limitations, not device power consumption) RATING -65 to +150 -0.5 to +13 -0.5 to +6.5 5.0 1.0 UNIT C V V mA W
NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.
DEVICE SPECIFICATIONS
SUPPLY VOLTAGE (V) TYPE P87C552-4 P87C552-5 MIN 4.5 4.5 MAX 5.5 5.5 FREQUENCY (MHz) MIN 3.5 3.5 MAX 16 16 TEMPERATURE RANGE (C) 0 to +70 -40 to +85
1998 May 01
7
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
87C552
DC ELECTRICAL CHARACTERISTICS
VSS, AVSS = 0V SYMBOL IDD IID IPD Inputs VIL VIL1 VIL2 VIH VIH1 VIH2 IIL ITL IIL1 IIL2 IIL3 Outputs VOL VOL1 VOL2 VOH Output low voltage, ports 1, 2, 3, 4, except P1.6, P1.7 Output low voltage, port 0, ALE, PSEN, PWM0, PWM1 Output low voltage, P1.6/SCL, P1.7/SDA Output high voltage, ports 1, 2, 3, 4, except P1.6/SCL, P1.7/SDA -IOH = 60A -IOH = 25A -IOH = 10A VOH1 Output high voltage (port 0 in external bus mode, ALE, PSEN, PWM0, PWM1)8 -IOH = 400A -IOH = 150A -IOH = 40A -IOH = 400A -IOH = 120A Test freq = 1MHz, Tamb = 25C 2.4 0.75VDD 0.9VDD 2.4 0.75VDD 0.9VDD 2.4 0.8VDD 50 150 10 V V V V V V V V k pF IOL = 1.6mA7 IOL = 3.2mA7 0.45 0.45 0.4 V V V Input low voltage, except EA, P1.6, P1.7 Input low voltage to EA Input low voltage to P1.6/SCL, P1.7/SDA5 -0.5 -0.5 -0.5 0.2VDD+0.9 0.7VDD 0.7VDD VIN = 0.45V See note 6 0.45V < VI < VDD 0V < VI < 6V 0V < VDD < 5.5V 0.45V < VI < VDD 0.2VDD-0.1 0.2VDD-0.3 0.3VDD VDD+0.5 VDD+0.5 6.0 -50 -650 10 10 1 V V V V V V A A A A A PARAMETER Supply current operating: PCA8XC552-5-16 Idle mode: 87C552 Power-down current: 87C552 TEST CONDITIONS See notes 1 and 2 fOSC = 16MHz See notes 1 and 3 fOSC = 16MHz See notes 1 and 4; 2V < VPD < VDD max LIMITS MIN MAX 40 7 50 UNIT mA mA A
Input high voltage, except XTAL1, RST Input high voltage, XTAL1, RST Input high voltage, P1.6/SCL, P1.7/SDA5 Logical 0 input current, ports 1, 2, 3, 4, except P1.6, P1.7 Logical 1-to-0 transition current, ports 1, 2, 3, 4, except P1.6, P1.7 Input leakage current, port 0, EA, STADC, EW Input leakage current, P1.6/SCL, P1.7/SDA Input leakage current, port 5
IOL = 3.0mA7
VOH2 RRST CIO
Output high voltage (RST) Internal reset pull-down resistor Pin capacitance
Analog Inputs AVDD AIDD AIID AIPD Analog supply voltage: 87C5529 Analog supply current: operating: Idle mode: 87C552 Power-down mode: 87C552 2V < AVPD < AVDD max 50 AVDD = VDD0.2V Port 5 = 0 to AVDD 4.5 5.5 1.2 50 V mA A A
1998 May 01
8
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
87C552
DC ELECTRICAL CHARACTERISTICS (Continued)
TEST SYMBOL Analog Inputs (Continued) AVIN AVREF Analog input voltage Reference voltage: AVREF- AVREF+ Resistance between AVREF+ and AVREF- Analog input capacitance Sampling time Conversion time (including sampling time) Differential non-linearity10, 11, 12 Integral non-linearity10, 13 Offset error10, 14 error10, 16 517 Gain error10, 15 Absolute voltage AVSS-0.2 AVSS-0.2 AVDD+0.2 10 50 15 8tCY 50tCY 1 2 2 0.4 3 1 AVDD+0.2 V V V k pF s s LSB LSB LSB % LSB LSB PARAMETER CONDITIONS MIN LIMITS MAX UNIT
RREF CIA tADS tADC DLe ILe OSe Ge Ae MCTC
Channel to channel matching
Ct Crosstalk between inputs of port 0-100kHz -60 dB NOTES FOR DC ELECTRICAL CHARACTERISTICS: 1. See Figures 10 through 15 for IDD test conditions. 2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10ns; VIL = VSS + 0.5V; VIH = VDD - 0.5V; XTAL2 not connected; EA = RST = Port 0 = EW = VDD; STADC = VSS. 3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10ns; VIL = VSS + 0.5V; VIH = VDD - 0.5V; XTAL2 not connected; Port 0 = EW = VDD; EA = RST = STADC = VSS. 4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = EW = VDD; EA = RST = STADC = XTAL1 = VSS. 5. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I2C specification, so an input voltage below 1.5V will be recognized as a logic 0 while an input voltage above 3.0V will be recognized as a logic 1. 6. Pins of ports 1 (except P1.6, P1.7), 2, 3, and 4 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 7. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5mA and no more than two outputs exceed the test conditions. 8. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VDD specification when the address bits are stabilizing. 9. The following condition must not be exceeded: VDD - 0.2V < AVDD < VDD + 0.2V. 10. Conditions: AVREF- = 0V; AVDD = 5.0V. Measurement by continuous conversion of AVIN = -20mV to 5.12V in steps of 0.5mV, derivating parameters from collected conversion results of ADC. AVREF+ (87C552) = 4.977V. ADC is monotonic with no missing codes. 11. The differential non-linearity (DLe) is the difference between the actual step width and the ideal step width. (See Figure 1.) 12. The ADC is monotonic; there are no missing codes. 13. The integral non-linearity (ILe) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset error. (See Figure 1.) 14. The offset error (OSe) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and a straight line which fits the ideal transfer curve. (See Figure 1.) 15. The gain error (Ge) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error), and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. (See Figure 1.) 16. The absolute voltage error (Ae) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. 17. This should be considered when both analog and digital signals are simultaneously input to port 5.
1998 May 01
9
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
87C552
Offset error OSe
Gain error Ge
1023
1022
1021
1020
1019
1018 (2)
7 Code Out 6 (1)
5 (5) 4 (4) 3 (3) 2
1
1 LSB (ideal)
0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024
AVIN (LSBideal) Offset error OSe (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential non-linearity (DLe). (4) Integral non-linearity (ILe). (5) Center of a step of the actual transfer curve.
1 LSB =
AVREF+
- AVREF-
1024
SU00212
Figure 1. ADC Conversion Characteristic
1998 May 01
10
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
87C552
AC ELECTRICAL CHARACTERISTICS1, 2
12MHz CLOCK SYMBOL 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tAVLL tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tDW tWHQX tRLAZ tWHLH External Clock tCHCX tCLCX tCLCH tCHCL tXLXL tQVXH tXHQX tXHDX 5 5 5 5 6 6 6 6 High time3 Low time3 Rise time3 Fall time3 1.0 700 50 0 20 20 20 20 0.75 492 8 0 20 20 20 20 12tCLCL 10tCLCL-133 2tCLCL-117 0 10tCLCL-133 20 20 20 20 ns ns ns ns s ns ns ns ns 3, 4 3 3 3 3 3 3 3 3, 4 3, 4 4 4 4 4 3, 4 Address valid to ALE low RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data before WR Data hold after WR RD low to address float RD or WR high to ALE high 43 200 203 23 433 33 0 123 23 0 97 517 585 300 138 120 3 288 13 0 103 tCLCL-40 43 400 400 252 0 55 350 398 238 3tCLCL-50 4tCLCL-130 tCLCL-60 7tCLCL-150 tCLCL-50 0 tCLCL+40 23 275 275 148 0 2tCLCL-70 8tCLCL-150 9tCLCL-165 3tCLCL+50 tCLCL-40 6tCLCL-100 6tCLCL-100 5tCLCL-165 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns FIGURE 2 2 2 2 2 2 2 2 2 2 2 2 PARAMETER Oscillator frequency ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float 0 59 312 10 43 205 145 0 38 208 10 127 28 48 234 23 143 83 0 tCLCL-25 5tCLCL-105 10 85 8 28 150 tCLCL-40 3tCLCL-45 3tCLCL-105 MIN MAX 16MHz CLOCK MIN MAX VARIABLE CLOCK MIN 3.5 2tCLCL-40 tCLCL-55 tCLCL-35 4tCLCL-100 MAX 16 UNIT MHz ns ns ns ns ns ns ns ns ns ns ns
Serial Timing - Shift Register Mode4 (Test Conditions: Tamb = 0C to +70C; VSS = 0V; Load Capaciatnce = 80pF) Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge
tXHDV 6 Clock rising edge to input data valid 700 492 NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. tCLCL = 1/fOSC = one oscillator clock period. tCLCL = 83.3ns at fOSC = 12MHz. tCLCL = 62.5ns at fOSC = 16MHz. 4. These values are characterized but not 100% production tested.
1998 May 01
11
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
87C552
AC ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL PARAMETER INPUT OUTPUT
I2C Interface (Refer to Figure 9)5 tHD;STA tLOW tHIGH tRC tFC tSU;DAT1 tSU;DAT2 tSU;DAT3 tHD;DAT tSU;STA tSU;STO tBUF tRD START condition hold time SCL low time SCL high time SCL rise time SCL fall time Data set-up time SDA set-up time (before rep. START cond.) SDA set-up time (before STOP cond.) Data hold time Repeated START set-up time STOP condition set-up time Bus free time SDA rise time 14 tCLCL 16 tCLCL 14 tCLCL 1s 0.3s 250ns 250ns 250ns 0ns 14 tCLCL 14 tCLCL 14 tCLCL 1s > 4.0s 1 > 4.7s 1 > 4.0s 1 -2 < 0.3s 3 > 20 tCLCL - tRD > 1s 1 > 8 tCLCL > 8 tCLCL - tFC > 4.7s 1 > 4.0s 1 > 4.7s 1 -2
tFD SDA fall time 0.3s < 0.3s 3 NOTES: 1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s. 2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1s. 3. Spikes on the SDA and SCL lines with a duration of less than 3 tCLCL will be filtered out. Maximum capacitance on bus-lines SDA and SCL = 400pF. 4. tCLCL = 1/fOSC = one oscillator clock period at pin XTAL1. For 62ns (42s) < tCLCL < 285ns (16MHz (24Hz) > fOSC > 3.5MHz) the SI01 interface meets the I2C-bus specification for bit-rates up to 100 kbit/s. 5. These values are guaranteed but not 100% production tested.
1998 May 01
12
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
87C552
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always `t' (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A - Address C - Clock D - Input data H - Logic level high I - Instruction (program memory contents) L - Logic level low, or ALE P - PSEN Q - Output data R - RD signal t - Time V - Valid W - WR signal X - No longer a valid logic level Z - Float Examples: tAVLL = Time for address valid to ALE low. tLLPL = Time for ALE low to PSEN low.
tLHLL
ALE
tAVLL
tLLPL
PSEN
tPLPH tLLIV tPLIV tPLAZ tPXIX
INSTR IN
tLLAX
tPXIZ
PORT 0
A0-A7
A0-A7
tAVIV
PORT 2 A0-A15 A8-A15
SU00006
Figure 2. External Program Memory Read Cycle
ALE
tWHLH
PSEN
tLLDV tLLWL
RD
tRLRH
tAVLL
PORT 0
tLLAX tRLAZ
A0-A7 FROM RI OR DPL
tRLDV tRHDX
DATA IN
tRHDZ
A0-A7 FROM PCL
INSTR IN
tAVWL tAVDV
PORT 2 P2.0-P2.7 OR A8-A15 FROM DPH A0-A15 FROM PCH
SU00007
Figure 3. External Data Memory Read Cycle
1998 May 01
13
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
87C552
ALE
tWHLH
PSEN
tLLWL
WR
tWLWH
tAVLL
PORT 0
tLLAX
A0-A7 FROM RI OR DPL
tQVWX tDW
DATA OUT
tWHQX
A0-A7 FROM PCL
INSTR IN
tAVWL
PORT 2
P2.0-P2.7 OR A8-A15 FROM DPH
A8-A15 FROM PCH
SU00213
Figure 4. External Data Memory Write Cycle
tHIGH VIH1
0.8V
tr VIH1
0.8V
tf VIH1 VIH1
0.8V
0.8V
tLOW tCLCL
SU00214
Figure 5. External Clock Drive XTAL1
INSTRUCTION ALE
0
1
2
3
4
5
6
7
8
tXLXL
CLOCK
tQVXH
OUTPUT DATA 0 WRITE TO SBUF
tXHQX
1 2 3 4 5 6 7
tXHDV
INPUT DATA VALID CLEAR RI VALID
tXHDX
SET TI VALID VALID VALID VALID VALID VALID
SET RI
SU00027
Figure 6. Shift Register Mode Timing
1998 May 01
14
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
87C552
2.4V 2.0V Test Points 0.8V 0.45V NOTE: AC inputs during testing are driven at 2.4V for a logic `1' and 0.45V for a logic `0'. Timing measurements are made at 2.0V for a logic `1' and 0.8V for a logic `0'. 0.8V 2.0V
SU00215
Figure 7. AC Testing Input/Output
Float 2.4V 2.0V 0.8V 2.0V 0.8V 2.4V
0.45V
0.45V
NOTE: The float state is defined as the point at which a port 0 pin sinks 3.2mA or sources 400A at the voltage test levels.
SU00216
Figure 8. AC Testing Input, Float Waveform
repeated START condition START or repeated START condition tRD STOP condition 0.7 VCC 0.3 VCC tBUF tFD tRC tFC tSU;STO 0.7 VCC 0.3 VCC tSU;DAT3 tHD;STA tLOW tHIGH tSU;DAT1 tHD;DAT tSU;DAT2 tSU;STA START condition
SDA (INPUT/OUTPUT)
SCL (INPUT/OUTPUT)
SU00107A
Figure 9. Timing SIO1 (I2C) Interface
1998 May 01
15
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
87C552
50 (1) 40
30 IDD mA 20 (2)
10
(3) (4)
0 NOTE: These values are valid only within the frequency specifications of the device under test. 0 4 8 f (MHz) 12 16
(1) (2) (3) (4)
Maximum operating mode; VDD = 6V Maximum operating mode; VDD = 4V Maximum idle mode; VDD = 6V Maximum idle mode; VDD = 4V
SU00217
Figure 10. 16MHz Version Supply Current (IDD) as a Function of Frequency at XTAL1 (fOSC)
VDD
VDD IDD P1.6 P1.7 VDD P0 EA EW VDD VDD
RST STADC (NC) CLOCK SIGNAL XTAL2 XTAL1
AVSS VSS AVref-
SU00218
Figure 11. IDD Test Condition, Active Mode All other pins are disconnected1 1. Active Mode: a. The following pins must be forced to VDD: EA, RST, Port 0, and EW. b. The following pins must be forced to VSS: STADC, AVss, and AVref-. c. Ports 1.6 and 1.7 should be connected to VDD through resistors of sufficiently high value such that the sink current into these pins cannot exceed the IOL1 spec of these pins. d. The following pins must be disconnected: XTAL2 and all pins not specified above.
1998 May 01
16
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
87C552
VDD
VDD IDD P1.6 P1.7 RST STADC P0 VDD VDD
(NC) CLOCK SIGNAL
XTAL2 XTAL1
EW EA AVSS
VSS
AVref-
SU00219
Figure 12. IDD Test Condition, Idle Mode All other pins are disconnected2 2. Idle Mode: a. The following pins must be forced to VDD: Port 0 and EW. b. The following pins must be forced to VSS: RST, STADC, AVss,, AVref-, and EA. c. Ports 1.6 and 1.7 should be connected to VDD through resistors of sufficiently high value such that the sink current into these pins cannot exceed the IOL1 spec of these pins. These pins must not have logic 0 written to them prior to this measurement. d. The following pins must be disconnected: XTAL2 and all pins not specified above.
VDD-0.5 0.5V
0.7VDD 0.2VDD-0.1
tCHCL
tCLCX tCLCL
tCHCX tCLCH
SU00220
Figure 13. Clock Signal Waveform for IDD Tests in Active and Idle Modes tCLCH = tCHCL = 5ns
VDD P1.6 P1.7 RST STADC P0 VDD IDD VDD VDD
(NC)
XTAL2 XTAL1 VSS
EW EA AVSS AVref-
SU00221
Figure 14. IDD Test Condition, Power Down Mode All other pins are disconnected. VDD = 2V to 5.5V3 3. Power Down Mode: a. The following pins must be forced to VDD: Port 0 and EW. b. The following pins must be forced to VSS: RST, STADC, XTAL1, AVss,, AVref-, and EA. c. Ports 1.6 and 1.7 should be connected to VDD through resistors of sufficiently high value such that the sink current into these pins cannot exceed the IOL1 spec of these pins. These pins must not have logic 0 written to them prior to this measurement. d. The following pins must be disconnected: XTAL2 and all pins not specified above.
1998 May 01
17
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
87C552
EPROM CHARACTERISTICS
The 87C552 is programmed by using a modified Quick-Pulse ProgrammingTM algorithm. It differs from older methods in the value used for VPP (programming supply voltage) and in the width and number of the ALE/PROG pulses. The 87C552 contains two signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes identify the device as an 87C552 manufactured by Philips. Table 3 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the lock bits. The circuit configuration and waveforms for quick-pulse programming are shown in Figures 15 and 16. Figure 17 shows the circuit configuration for normal program memory verification.
programmed, further programming of the code memory and encryption table is disabled. However, the other lock bit can still be programmed. Note that the EA/VPP pin must not be allowed to go above the maximum specified VPP level for any amount of time. Even a narrow glitch above that voltage can cause permanent damage to the device. The VPP source should be well regulated and free of glitches and overshoot.
Program Verification
If lock bit 2 has not been programmed, the on-chip program memory can be read out for program verification. The address of the program memory locations to be red is applied to ports 1 and 2 as shown in Figure 17. The other pins are held at the "Verify Code Data" levels indicated in Table 3. The contents of the address location will be emitted on port 0. External pull-ups are required on port 0 for this operation. If the encryption table has been programmed, the data presented at port 0 will be the exclusive NOR of the program byte with one of the encryption bytes. The user will have to know the encryption table contents in order to correctly decode the verification data. The encryption table itself cannot be read out. Reading the Signature Bytes The signature bytes are read by the same procedure as a normal verification of locations 030H and 031H, except that P3.6 and P3.7 need to be pulled to a logic low. The values are: (030H) = 15H indicates manufactured by Philips Components (031H) = 94H indicates 87C552
Quick-Pulse Programming
The setup for microcontroller quick-pulse programming is shown in Figure 15. Note that the 87C552 is running with a 4 to 6MHz oscillator. The reason the oscillator needs to be running is that the device is executing internal address and program data transfers. The address of the EPROM location to be programmed is applied to ports 1 and 2, as shown in Figure 15. The code byte to be programmed into that location is applied to port 0. RST, PSEN, and pins of ports 2 and 3 specified in Table 3 are held at the "Program Code Data" levels indicated in Table 3. The ALE/PROG is pulsed low 25 times as shown in Figure 16. To program the encryption table, repeat the 25-pulse programming sequence for addresses 0 through 1FH, using the "Pgm Encryption Table" levels. Do not forget that after the encryption table is programmed, verification cycles will produce only encrypted data. To program the lock bits, repeat the 25-pulse programming sequence using the "Pgm Lock Bit" levels. After one lock bit is
Program/Verify Algorithms
Any algorithm in agreement with the conditions listed in Table 3, and which satisfies the timing specifications, is suitable.
Table 3. EPROM Programming Modes
MODE Read signature Program code data Verify code data Pgm encryption table Pgm lock bit 1 RST 1 1 1 1 1 PSEN 0 0 0 0 0 ALE/PROG 1 0* 1 0* 0* EA/VPP 1 VPP 1 VPP VPP P2.7 0 1 0 1 1 P2.6 0 0 0 0 1 P3.7 0 1 1 1 1 P3.6 0 1 1 0 1
Pgm lock bit 2 1 0 0* VPP 1 1 0 0 NOTES: 1. 0 = Valid low for that pin; 1 = valid high for that pin. 2. VPP = 12.75V 0.25V. 3. VDD = 5V 10% during programming and verification. * ALE/PROG receives 25 programming pulses while VPP is held at 12.75V. Each programming pulse is low for 100s (10s) and high for a minimum of 10s.
TMTrademark phrase of Intel Corporation. 1998 May 01 18
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
87C552
+5V
VDD A0-A7 1 1 1 P1 RST P3.6 P3.7 XTAL2 4-6MHz XTAL1 VSS 87C552 P0 PGM DATA +12.75V 25 100s PULSES TO GROUND 0 1 0 A8-A12
EA/VPP ALE/PROG PSEN P2.7 P2.6 P2.0-P2.4
SU00222
Figure 15. Programming Configuration
1 ALE/PROG: 0
25 PULSES
1 ALE/PROG: 0
10s MIN
100s+10
SU00018
Figure 16. PROG Waveform
+5V
VDD A0-A7 1 1 1 P1 RST P3.6 P3.7 XTAL2 4-6MHz XTAL1 VSS 87C552 P0 PGM DATA 1 1 0 0 ENABLE 0 A8-A12
EA/VPP ALE/PROG PSEN P2.7 P2.6 P2.0-P2.4
SU00223
Figure 17. Program Verification
1998 May 01
19
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
87C552
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
Tamb = 21C to +27C, VDD = 5V10%, VSS = 0V SYMBOL VPP IPP 1/tCLCL tAVGL tGHAX tDVGL tGHDX tEHSH tSHGL tGHSL tGLGH tAVQV tELQZ tEHQZ tGHGL PARAMETER Programming supply voltage Programming supply current Oscillator frequency Address setup to PROG low Address hold after PROG Data setup to PROG low Data hold after PROG P2.7 (ENABLE) high to VPP VPP setup to PROG low VPP hold after PROG PROG width Address to data valid ENABLE low to data valid Data float after ENABLE PROG high to PROG low 0 10 4 48tCLCL 48tCLCL 48tCLCL 48tCLCL 48tCLCL 10 10 90 110 48tCLCL 48tCLCL 48tCLCL s s s s MIN 12.5 MAX 13.0 50 6 UNIT V mA MHz
PROGRAMMING* P1.0-P1.7 P2.0-P2.4 ADDRESS
VERIFICATION* ADDRESS
tAVQV
PORT 0 DATA IN DATA OUT
tDVGL tAVGL
ALE/PROG
tGHDX tGHAX
tGLGH tSHGL
tGHGL tGHSL
LOGIC 1 EA/VPP LOGIC 0
LOGIC 1
tEHSH
P2.7 ENABLE
tELQV
tEHQZ
SU00020
* FOR PROGRAMMING VERIFICATION SEE FIGURE 17. FOR VERIFICATION CONDITIONS SEE TABLE 3.
Figure 18. EPROM Programming and Verification
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011.
1998 May 01
20
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
87C552
PLCC68: plastic leaded chip carrier; 68 leads; pedestal
SOT188-3
1998 May 01
21
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
87C552
QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SOT318-2
1998 May 01
22
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
87C552
NOTES
1998 May 01
23
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
87C552
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Date of release: 05-98 Document order number: 9397 750 05367
Philips Semiconductors
1998 May 01 24

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